IPNoSys III:SDN Paradigm in a non-conventional NoC-based Processor / IPNoSys III: O Paradigma SDN em uma NoC Baseada em um Processador Não Convencional

Denis Freire Lopes Nunes, Sílvio Roberto Fernandes de Araújo, Márcio Eduardo Kreutz

Abstract


Dynamic resource allocation has a significant impact on the performance of MPSoCs (Multiprocessors System-on-Chip) based on Networks-on-Chip (NoCs). In this work, we propose the IPNoSys III, an NoC using Software Defined Networks (SDN) paradigm applied to IPNoSys, a parallel non-conventional architecture. IPNoSys III has a 2D mesh topology, that contains in each node four processing cores, connected to a memory and that run packages in the IPNoSys format, and a communication unit. An SDN controller, connected to all nodes, manages the network and has an overview of the network to execute the routing algorithm and to map tasks according to the performance objectives. The results show up to 17% better performance in clock cycles to the SDN controller than a static solution and up to 46% better when comparing IPNoSys III to a conventional NoC.

 

 


Keywords


IPNoSys, NoC, MPSoCs, SDNoCs.

Full Text:

PDF

References


C. A. Zeferino and A. A. Susin, “SoCIN: a parametric and scalable network-on-chip,” in 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings., 2003, pp. 169–174, doi: 10.1109/SBCCI.2003.1232824.

L. Benini and G. De Micheli, “Networks on chips: a new SoC paradigm,” Computer (Long. Beach. Calif)., vol. 35, no. 1, pp. 70–78, 2002, doi: 10.1109/2.976921.

Intel, “Teraflops Research Chip,” 2019. https://www.intel.com/pressroom/kits/Teraflops/index.htm (accessed May 01, 2019).

Tilera, “TILE-Gx72 Processor,” 2019. http://www.mellanox.com/page/products_dyn?product_family=238&mtag=tile_gx72 (accessed May 01, 2019).

L. Soares, P. Dziurzanski, and A. K. Singh, Dynamic Resource Allocation in Embedded, High-Performance and Cloud Computing. River Publishers, 2016.

N. Dutt, A. Jantsch, and S. Sarma, “Self-aware Cyber-Physical Systems-on-Chip,” in 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2015, pp. 46–50, doi: 10.1109/ICCAD.2015.7372548.

D. Kreutz, F. M. V. Ramos, P. E. Verissimo, C. E. Rothenberg, S. Azodolmolky, and S. Uhlig, “Software-defined networking: A comprehensive survey,” Proc. IEEE, vol. 103, no. 1, pp. 14–76, Jun. 2015, doi: 10.1109/JPROC.2014.2371999.

H. Kim and N. Feamster, “Improving network management with software defined networking,” IEEE Commun. Mag., vol. 51, no. 2, pp. 114–119, Feb. 2013, doi: 10.1109/MCOM.2013.6461195.

Y. Luo, P. Cascon, E. Murray, and J. Ortega, “Accelerating OpenFlow switching with network processors,” in Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems - ANCS ’09, 2009, p. 70, doi: 10.1145/1882486.1882504.

S. Deb, A. Ganguly, P. P. Pande, B. Belzer, and D. Heo, “Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 2, no. 2, pp. 228–239, Jun. 2012, doi: 10.1109/JETCAS.2012.2193835.

L. Cong, W. Wen, and W. Zhiying, “A configurable, programmable and software-defined network on chip,” in 2014 IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA), Sep. 2014, pp. 813–816, doi: 10.1109/WARTIA.2014.6976396.

X. Zhou and Z. Zhu, “A dynamic task mapping algorithm for SDNoC,” Microelectronics J., vol. 63, pp. 58–65, May 2017, doi: 10.1016/j.mejo.2017.03.003.

A. Scionti, S. Mazumdar, and A. Portero, “Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud,” Sensors, vol. 18, no. 7, p. 24, Jul. 2018, doi: 10.3390/s18072330.

P. Dzhunev, “Improving Network Monitoring with Software Defined Networking,” IEEE Commun. Mag., vol. 46, pp. 114–119, 2013, [Online]. Available: https://inis.iaea.org/search/search.aspx?orig_q=RN:46130071.

S. R. Fernandes, B. C. Oliveira, and I. S. Silva, “Using NoC routers as processing elements,” in Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design Chip on the Dunes - SBCCI ’09, 2009, vol. 24, p. 1, doi: 10.1145/1601896.1601927.

T. R. B. S. Soares, I. S. Silva, and S. R. Fernandes, “IPNoSys II: A New Architecture for IPNoSys Programming Model,” in Proceedings of the 28th Symposium on Integrated Circuits and Systems Design - SBCCI ’15, 2015, pp. 1–7, doi: 10.1145/2800986.2801012.

J. Wang, M. Zhu, C. Peng, L. Zhou, Y. Qian, and W. Dou, “Software-Defined Photonic Network-on-Chip,” in The Third International Conference on e-Technologies and Networks for Development (ICeND2014), Apr. 2014, pp. 127–130, doi: 10.1109/ICeND.2014.6991365.

S. Ellinidou, G. Sharma, T. Rigas, T. Vanspouwen, O. Markowitch, and J. Dricot, “SSPSoC: A Secure SDN-Based Protocol over MPSoC,” Secur. Commun. Networks, vol. 2019, p. 11, Mar. 2019, doi: 10.1155/2019/4869167.

S. R. Fernandes, B. C. Oliveira, M. Costa, and I. S. Silva, “Processing while routing: a network-on-chip-based parallel system,” IET Comput. Digit. Tech., vol. 3, no. 5, pp. 525–538, 2009, doi: 10.1049/iet-cdt.2008.0071.

S. R. F. de Araújo, “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip – Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys,” Tese de Doutorado, Universidade Federal do Rio Grande do Norte, 2012.

I. A. de S. Moura, “Proposta , Validação e Avaliação Qualitativa de uma Arquitetura MPSoC Baseada Nos Elementos de Processamento de IPNoSys II,” 2020.

L. Duenha, H. Almeida, M. Guedes, M. Boy, and R. Azevedo, “MPSoCBench: A Toolset for MPSoC System Level Evaluation,” 2014, [Online]. Available: http://archc.lsc.ic.unicamp.br/benchs/mpsocbench/index.html.




DOI: https://doi.org/10.34117/bjdv7n1-159

Refbacks

  • There are currently no refbacks.